Instruction Set Architecture (ISA) together with processor architecture defines a software view of processor family as seen by programmer. It has prevailing impact on several key processor characteristics, including code density and ease of software development.
The BA2x ISA was designed from ground up with design goal achieving highest code density among 32-bit processors with no compromise on performance. To achieve such ambitious goal it was necessary to rethink how ISA is designed. Often instruction set is defined with legacy constraints and by processor architects who are coming from hardware background. We have instead dropped all legacy constraints and first developed a fully working and optimized compiler for initial ISA proposal. This allowed us to do conclusive benchmarking on vast code base, comparing results with other architectures and finding new, better solutions.
Ultimately, ISA design is an optimization problem. Iterating through numerous approaches, ideas, optimizations and also dead ends we finally settled on BA2x ISA that is (based on our benchmarks) best fulfilling our design goal of highest code density at no compromise on performance.
The resulting BA2x ISA has 32 general purpose registers, all addressable with all register operand instructions. It also features cleverly encoded 16-bit, 24-bit, 32-bit and 48-bit instructions for maximum code density with simple decoding.
The smaller the processor, the more ISA matters. Best example of BA2x ISA is Beyond BA20 PipelineZero processor, capable of outstanding performance per MHz at extremely small area and ultra-low power consumption.
Code density
Reducing ASIC power and cost
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- Highest code density among 32-bit and 64-bit processors without compromise on performance
- Often better code density than with legacy 8-bit and 16-bit processors, like 8051 and 80251.
- Smaller memories burn less power, especially important when on-die memories often consume more power than processor itself.
- In case of embedded processors, memories are usually bigger than processor core itself.
- Code density is achieved by reducing instruction count instead of reducing the average instruction size.
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Ease-of-use |
- Programming in assembly is usually not required. When it is, instructions take 32-bit immediates, and assembler automatically selects shortest one unless specifically instructed otherwise.
- Instructions have no strange side effects. All instructions with register operands can address any of 32 general purpose registers.
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Performance
32 GPRs, small static instruction count
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- Code compiled into BA2x ISA usually results in 10% - 40% smaller static instruction count than competing architectures.
- 32 general purpose registers reduce chance of register spills (saving and restoring temporary data to stack, due to lack of available registers), more chances to unroll loops…
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Extensibility |
- More then 40% of instruction space is available for instruction set extensions (~25 % will be always left for custom instructions)
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