Beyond Semiconductor
Beyond General Purpose Debug Interface Controller


The Debug Interface Controller is designed to provide access to internal processor debug and/or WISHBONE bus resources using industry standard IEEE 1149.1-2001 Test Access Port protocol. Paired with any standard TAP controller, the debug interface will enable access to internal resources using off the shelf hardware and software, such as JTAG key and gdb to name the most commonly used combination.
Modular design supports seamless integration into systems implementing different clock, reset and power domains.
Debug interface can be used in virtually any embedded system that uses standard bus interconnect other than WISHBONE, if simple protocol converters are added.
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TAP Interface
  • Uses decoded instruction register value and state information from IEEE 1149.1-2001 External TAP Controller to shift and load its data register appropriately
  • Command and data are transmitted and received serially
  • 80-bit data register (DR) stores all the information needed to execute debugging commands
  • 8-bit CRC for added robustness generated and checked as part of DR
  • WISHBONE Module selection logic
  • Deadlock prevention allows independent reset assertion and/or clock gating per bus module. Keeping or initializing state information is thus not necessary in external HW/SW
 
 
WISHBONE Modules
  • Up to 16 Bus modules (WISHBONE interfaces), compile time definable
  • Bus module includes:
    • WISHBONE SoC Interface Rev. B3 compliant
    • Optional control signals for Debug Unit of Beyond BA processors
  • Bus module can be connected to the Debug Unit of Beyond BA processor or to internal bus infrastructure
  • Each bus module operates on its own clock and reset domain
  • Full clock domain crossing synchronization
 
 


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