Beyond UART (Universal Asyncchronous Receiver/Transmitter) 16550 Serial Controller IP core translates data between parallel and serial interfaces, and adds/removes start,stop bits, and optionally parity bit. It can be used to communicate with other external devices using a serial cable and RS232 protocol. This core is fully compatible with industry standard National Semiconductors 16550D device except for scratch regiser which is not implemented. Additionaly CPU can read values of divisor latch and fill levels of transmitter and receiver FIFOs. On power up/reset Beyond UART starts in 16450 mode.

• Compatible with PC16550D / 16450
• FIFO depth of 16 bytes in 16650 mode
• Modem control functions
• Programmable serial interface
• Number of data bits (5 - 8)
• Number of stop bits
• 1 and 1, 5 for (5 data bits)
• 1 and 2 (6, 7, 8 data bits)
• False start bit detection
• Internal diagnostic (loopback, error simulation)
• Line break generation and detection
• Prioritized interrupts
• Readable Divisor latch value
• Readable transmitter and receiver FIFO fill levels

Supported SoC Bus Interfaces

The core is available with support for any of the following interconnect options:

• AMBA:
• APB Slave Interface
• WISHBONE Slave Rev. B.3 compliant interfaces
• Other buses: for additional options please contact sales@beyondsemi.com

Block diagram shows the general architecture of the Beyond UART 16550 Serial Controller IP core. It consists of following building blocks:

• Bus interface
• Modem control logic
• Internal registers
• Transmitter logic
• FIFO / THR register
• TX shift register
• Receiver logic
• FIFO / RBR register
• RX shift register

• Full Verilog RTL source
• Extensive Test Bench
• Documentation
• Linux driver
  
• Free Engineering support

• Networking
• Embedded
• Portable and wireless
• Home entertainment consumer electronics