Beyond Semiconductor - Beyond Debug Interface Controller

Beyond Debug Interface Controller

Introduction

The Beyond Debug Interface Controller is connected on one side to the IEEE 1149.1-2001 Beyond TAP Controller as External scan chain Debug Interface register and on the other side to the Debug Unit of Beyond BA processor(s) and/or Beyond peripheral interface cores. It synchronizes signals from all clock domains, while decoding Debug Interface instructions and translating data between serial and parallel interfaces.

Features

80-bit serial scan chain register interface to the IEEE 1149.1-2001 Beyond TAP Controller
8-bit CRC generation and checking
Up to 16 BUS modules (parallel interfaces) selected with define
Each BUS module has:

AHB or WISHBONE SoC Interface Rev. B3 compliant
Optional control signals for Debug Unit of Beyond BA processors

Each BUS module can be connected to the Debug Unit of Beyond BA processor(s) or to Beyond peripheral interface cores
Each BUS module can operate on different clock domain
Full clock domain crossing synchronization
Synchronization is built to prevent deadlock if/when any one of parallel interfaces goes to reset state or it's clock stops running

Architecture

Figure bellow shows the general architecture of the Beyond Debug Interface IP core. It consists of following building blocks:

Shift register and control for serial scan chain
8-bit CRC check and generation
Debug command decode
Write latch registers
Read latch registers
Synchronization control FSM
Synchronization module
Bus module

Easy and Quick Start

Deliverables

Soft core RTL in Verilog
Test bench in Verilog
Engineering support

Target Applications

Software uploading and debugging with the IEEE 1149.1-2001 Beyond TAP Controller
Beyond peripheral interface cores initialization with the IEEE 1149.1-2001 Beyond TAP Controller