• Ease of use
• Complete state-of-the-art GNU toolchain with many user-friendly IDEs
• Average assembly programmer will find instruction set very intuitive
• Relatively few instructions programmer needs to be aware of, toolchain always picks the most optimal instruction encoding
• No non-orthogonal instruction with hard to predict side effects
• No register windows
• Superior code density
• Code density in typical applications better then competition without any compromise on performance
• Smaller code size (everything else being equal) always has positive effect on power and performance
• Careful encoding of instructions allows for easier implementation of high performance implementations
• Comparing to competing RISC processors Beyond Architecture 2 features 10% - 40% smaller static instruction count. This can be used either for gaining performance or reducing power consumption
• Up to 32 general purpose registers comparing to 16 by other close competitors
• Optional special instructions that help performance (like low overhead looping instruction)
• Optional DSP instructions
• Optional SIMD instructions (not yet finalized)
• Smaller area & ease of integration and SOC verification
• Processor implementations will be available as synthesizable verilog
• Processor does not require data access to code sections
• Extensibility
• More then 40% of instruction space is available for instruction set extensions (~25 % will be always left for custom instructions)

The Beyond Architecture 2 includes the following principal features:

• A linear 32-bit logical address space with implementation-specific physical address space
• Simple to use, orthogonal instruction set architecture with industry leading code density in it's class
• Simple memory addressing modes
• Configurable general purpose register file (from 12 - 32 GPR)