The Beyond Architecture 1 defines the architecture for a family of synthesizable RISC microprocessor cores. The Beyond Architecture 1 allows for a spectrum of chip and system processors at a variety of price/performance points for a range of applications. It is a 32/64-bit load and store RISC architecture designed with emphasis on:

• Performance
• Simplicity
• Low power requirements
• Scalability

The Beyond Architecture 1 includes the following principal features:

• A linear, 32-bit or 64-bit logical address space with processor-specific physical address space
• Simple and uniform-length instruction formats featuring different instruction set extensions:
• Beyond Architecture 1 Basic Instruction Set (BA1BIS) with 32-bit wide instructions aligned on 32- bit boundaries in memory and operating on 32-bit data
• Beyond Architecture 1 Vector eXtension (BA1VX) with 32-bit wide instructions aligned on 32-bit boundaries in memory and operating on 64-bit wide vectors
• Beyond Architecture 1 Floating-point eXtension (BA1FX) with 32-bit wide instructions aligned on 32-bit boundaries in memory and operating on 32-bit and 64-bit floating-point data
• Two simple memory addressing modes, whereby memory address is calculated by:
• Addition of a register operand and a signed 16-bit immediate value
• Addition of a register operand and a signed 16-bit immediate value followed by update of the register operand with the calculated effective address
• Two register operands (or one register and a constant) for most instructions who then place the result in a third register
• Single 32-bit general purpose register file with 32 or less registers
• Branch delay slot for keeping the pipeline as full as possible
• Support for separate instruction and data caches/MMUs (Harvard architecture) or for unified instruction and data caches/MMUs (Stanford architecture)
• A flexible architecture definition that allows certain functions to be performed either in hardware or with the assistance of processor-specific software
• Number of different, separated exceptions simplifying exception model